Integrated circuits can undergo various tests. One such test detects Transition Delay Faults (TDFs) which result from the finite rise and fall times of the signals in the gates and from the propagation delays because of interconnects between the gates. Circuit timing and circuit propensity for TDFs need to be evaluated carefully to avoid errors in operation, and to determine the maximum clock frequency at which the circuit can operate.
As integrated circuits have become smaller, significantly faster, and more complicated, testing for TDFs has become more complicated. One of the principal reasons stems from the use of layers of clock gating logic, which decreases power consumption in the circuit by disabling portions of circuitry, for example, when flip flops are not changing states.
Most integrated circuits are capable of operating in a test mode that is distinct from the functional mode. FIG. 1 shows two flip flops 110 and 130 with circuitry, referred to for convenience as combinational logic 120, connected between them. The combinational logic 120 can be any number of things, depending on the functionality of the circuit, as known to those of working skill in the art. A circuit may have tens or even hundreds of thousands of circuit combinations like the one shown in FIG. 1.
In test mode, an automatic test pattern generator (ATPG) 140 can be used to shift known data into the flip flops 110 and 130. The ATPG 140 provides pseudorandom data, so as to permit exercising of the combinational logic 120 in a variety of ways. Because the combinational logic 120 is known, the outputs for a given set of inputs are predictable. This process of shifting data into the circuit sometimes is referred to as scan shifting. As an example of what may occur during test mode, the ATPG 140 may shift data into the first flip flop 110 so that the value at the output 114 of flip flop 110 will be known. The ATPG 140 may shift in data that results in a 1 being present at input 112 and a 0 being present at output 114. When the 0 at output 114 goes through the combinational logic 120, it may result in a 0 being present at input 132 of flip flop 130. After the data is shifted in, the circuit is put into capture mode and pulsed twice at normal operating frequency. The first pulse causes the 1 at input 112 of the first flop 110 to shift to the output 114. When the output 114 of the first flip flop 110 goes through the combinational logic 120 it may put a 1 at the input 132 of flip flop 130. The 0 previously at input 132 then shifts to output 134. On the second pulse, the 1 at input 132 shifts to output 134. The objective of this procedure is to cause every flip flop to go from 1 to 0 and 0 to 1 so that the TDFs can be detected.
FIG. 2a shows a portion of a conventional circuit containing clock gating logic. The portion of the circuit shown in FIG. 2a typically would be part of a larger circuit which might be under the control of a clock 250. Various aspects of the circuit's functionality can be tested by using an ATPG 240 to input pseudorandom data into the circuit during scan testing. The goal of scan testing is to use all the flip flops in the circuit in a way that allows errors to be detected. In the circuit of FIG. 2a, test enable (TE) ports 212 and 222 of clock gating cells 210 and 220 are connected to a test scan enable (TEST_SE) signal, which is controlled by the Tester Pin #1 260, when Scan Mode is active. The TEST_SE signal is also connected to the select input 236 of a Scan Flip-Flop 230. When the TEST_SE signal is held high, as it is during scan shifting, the clock is ungated and the Scan_IN (SI) input 232 on the Scan Flip-Flop 230 is selected. When the TEST_SE signal is held low, the clock is gated, and the functional input (D) 234 of the Scan Flip-Flop 230 is selected.
One known method of testing for TDFs involves shifting test data in while the TEST_SE signal is high. When shifting data in, it is common to clock the circuit at a lower frequency than the frequency used for normal operation. For example, a circuit that normally would function at 200 MHz might be clocked at 100 MHz during scan shifting. After the test data is shifted in, the TEST_SE signal is held low during the capture sequence so that the circuit can operate as if it were in functional mode. During the capture sequence, the clock will be pulsed twice at the normal operating frequency. After the capture sequence, the TEST_SE pin is then held high again while the test data is shifted out. The test data can then be compared to expected data in order to verify the correct functioning of the circuit.
FIGS. 3a-d provides a graphical representation of the TEST_SE signal and Clock signal during testing mode. During scan shifting (the load/unload phase) 310, test data is shifted into the circuit. This is done while the TEST_SE signal is held high, ungating the clock, and while the clock is being pulsed at a frequency lower than its normal operating frequency. Once the desired test data has been shifted in, the circuit enters capture mode 320, where TEST_SE is held low and the clock is pulsed at its normal operating frequency. After the circuit has been pulsed at normal speed, the circuit reenters scan shifting mode 330 so that the test data can be shifted out and compared to expected results. In a typical circuit, the shifting in of new data and shifting out of old data occurs simultaneously.
In this method of testing for TDFs, because the TEST_SE signal is held low during the capture sequence, the clock gating will depend on the pseudorandom data being entered at the EN ports 214 and 224. As FIGS. 3a-d illustrate, there are four possible combinations of clock pulses. Either both clock pulses will be low (FIG. 3a); the first pulse will be high while the second pulse is low (FIG. 3b); the first pulse will be low while the second pulse is high (FIG. 3c); or both will be high (FIG. 3d). Which of these combinations occurs in the circuitry depends on the pseudorandom data entered at the EN ports 214 and 224.
Two pulses at the operating frequency of the circuit are needed during the capture sequence in order to capture TDFs. One pulse is needed to setup a transition delay rise (i.e. going from 0 to 1), and a second pulse is needed to catch a transition delay fall (i.e. going from 1 to 0). For a simple circuit with only two gating cells, like the one shown in FIG. 2a, each cell must receive a 11 signal in order to pulse the clock twice. Therefore, a one-in-sixteen chance exists that the two clock pulses needed to capture the TDFs will be present at each clock gating cell (one-fourth probability that both pulses will be high at each gating cell; hence the one-in-sixteen chance). It can be seen that, for each additional gating cell added to the circuit, the probability of capturing the TDFs decreases exponentially. Most modern circuits now contain so many layers of clock gating cells that generating pseudorandom data capable of capturing all the TDFs is virtually impossible.
An alternate method for testing the circuit, as shown in FIG. 2b, is to connect the TE ports 212 and 222 of the clock gating cells 210 and 220 to scan mode, which ungates the clock and always generates the two clock pulses needed to test for TDFs. A limitation of this method, however, is that TDFs in the EN ports of the clock gating circuitry will not be captured. To increase TDF coverage, the TE ports on the clock gating cells 210 and 220 need to be easily controlled to allow two or more clock pulses during capture cycles and to also be able to observe the TDFs on the EN ports of the clock gating cell.